The present disclosure relates generally to Magnetoresistive Random Access Memories (MRAMs) and, more particularly, to segmented magnetic tunnel junction (MTJ) MRAM arrays.
MRAM is a non-volatile memory that may be used for long term data storage. A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each MTJ cell in the array is located at a cross point of a word line and a bit line.
Each MTJ cell generally includes a non-magnetic conductor forming a lower electrical contact, a pinned magnetic layer, a tunnel barrier layer positioned on the pinned layer, and a free magnetic layer positioned on the tunnel barrier layer with an upper contact on the free magnetic layer.
The pinned layer of magnetic material has a magnetic vector that is always pointed in the same direction. The magnetic vector of the free layer is free, but constrained by the physical size of the layer, to point in either of two directions. An MTJ cell is used by connecting it in a circuit such that current flows vertically through the cell from one of the layers to the other. The MTJ cell can be electrically represented as a resistor and the size of the resistance depends upon the orientation of the magnetic vectors. The MTJ cell generally has a relatively high resistance when the magnetic vectors are misaligned (e.g., point in opposite directions) and a relatively low resistance when the magnetic vectors are aligned. That is, an MTJ cell stores a bit of information as the relative orientation of the magnetizations of the fixed and variable magnetic materials. In other words, the magnetization of each memory cell at any given time assumes one of two stable orientations. These two stable orientations, referred to as “parallel” and “anti-parallel” magnetic orientation, represent logic values of “0” and “1,” for example. The resistance of an MTJ cell varies depending upon whether it stores a “0” or a “1” value. The relative orientation of the magnetizations of a selected memory cell (and, therefore, the logic state of the memory cell) may be read by sensing the resistance value of the selected memory cell.
However, current memory architectures are generally insufficient for the sensing techniques used to read such memory cells. For example, it may be difficult in existing architectures to adequately compensate for sneak currents that may render memory reads inaccurate or unreliable, or reading from a memory cell may require too many steps.
Accordingly, what is needed is an improved MRAM memory array that may be used to resolve the above-described issues.